
/*
**************************************************************************************************************
File:         ddr3_assertions.sv
Description:  Defines the assertions used in verifying the DDR3 interface
Author     :  Rohit Kulkarni
              Aditya Joshi
**************************************************************************************************************
*/
`include "package.sv"

module ddr3_assertions(
  DDR_bus IF, 
  input logic OP, 
  input logic [LOGICAL_ADDR_WIDTH-1:0] ADDR, 
  input logic start, 
  output logic done
);
  

property RASL2RASH;
 @(posedge IF.CK)
   $fell(IF.RAS) |-> ##(tRCD-1) $rose(IF.RAS);
endproperty
RASL2RASH_1: assert property(RASL2RASH);  
    
  
endmodule




